In order to save power, the core circuitry of a device, for example a microprocessor, usually operates on a predetermined lower voltage level, even though the device must communicate externally using an input/output (I/O) voltage level which is higher than the predetermined voltage used by the core of the device. For example, a microprocessor chip operates on logic levels of high (H) and low (L) having voltage levels of 3.3 volts (V) and 0 V, respectively, although the device is connected to a 5 V power rail for use in external communications. Typically, a level shifter converts the inner voltage levels of 0 V and 3.3 V used by a microprocessor chip to the output voltage levels of 0 V and 5 V. However, a voltage difference of 5V between gates and drains/sources of output transistors may easily break own the gate oxide and fail the device.
As shown in FIG. 1, a conventional inverter comprises a PMOS transistor 130 and an NMOS transistor 140 connected in series and may be used as an output buffer to drive an input/output circuit. A source of the PMOS transistor 130 is connected to an external power supply terminal 150 of 5V while a source of the NMOS transistor 140 is connected to an external ground voltage 160 of 0V. The drains of PMOS transistor 130 and NMOS transistor 140 are connected to an output node 120 to transmit an output signal. The gates of PMOS transistor 130 and NMOS transistor 140 are connected to an input node 110 to receive an input signal. When the input signal of 0V (logic low) is applied, the PMOS transistor 130 turns on and the NMOS transistor 140 turns off. The inverter outputs a signal of 5V (logic high). The voltage difference between the gate and the drain/source of the PMOS transistor 130 is 5V. When the input signal of 5V (logic high) is applied, the PMOS transistor 130 turns off and the NMOS transistor 140 turns on. The inverter outputs a signal of 0V (logic low). The voltage difference between the gate and the drain/source of the NMOS transistor 140 is 5V.
Typically, to avoid a gate oxide breakdown, the electric field across the gate oxide is required to be smaller than 5 MV/cm. Assuming that gate oxide is 80 angstroms in a modern semiconductor manufacturing process, a voltage difference of 5V results in an electric field of 6.25 MV/cm across the gate oxide, which causes a gate oxide breakdown.
One way to address this problem is to lower the voltage used as the logic high value of the input signal high which in turns lowers a voltage difference between the gate and the drain/source of output transistors. Using this lower voltage logic high also lowers the voltage difference between the external power supply connected to the source of the PMOS transistor 130 and the logic high input signal provided to the gate of the PMOS transistor 130 prevents the PMOS transistor 130 from turning completely off. A static current flowing from the external power terminal to the external ground is undesirable.